27 #define PARALLEL_DATA_OFFSET 0
29 #define PARALLEL_STATUS_OFFSET 1
31 #define PARALLEL_CONTROL_OFFSET 2
33 #define PARALLEL_REGISTER_SPAN 3
39 #define PP_ATN_OUT (Pdx->IecAtnOut)
40 #define PP_CLK_OUT (Pdx->IecClkOut)
41 #define PP_DATA_OUT (Pdx->IecDataOut)
42 #define PP_RESET_OUT (Pdx->IecResetOut)
45 #define PP_LP_IRQ 0x10
46 #define PP_LP_BIDIR 0x20
49 #define PP_ATN_IN (Pdx->IecAtnIn)
50 #define PP_CLK_IN (Pdx->IecClkIn)
51 #define PP_DATA_IN (Pdx->IecDataIn)
52 #define PP_RESET_IN (Pdx->IecResetIn)
55 #define PAR_PORT (Pdx->ParPortPortAddress + PARALLEL_DATA_OFFSET)
58 #define IN_PORT (Pdx->ParPortPortAddress + PARALLEL_STATUS_OFFSET)
61 #define OUT_PORT (Pdx->ParPortPortAddress + PARALLEL_CONTROL_OFFSET)
64 #define CBMIEC_SET(_set) do { DBG_ASSERT((_set) != 0); Pdx->IecOutBits|=(_set); WRITE_PORT_UCHAR(OUT_PORT,(UCHAR)(Pdx->IecOutEor ^ Pdx->IecOutBits)); } while (0)
66 #define CBMIEC_RELEASE(_rel) do { DBG_ASSERT((_rel) != 0); Pdx->IecOutBits&=~(_rel); WRITE_PORT_UCHAR(OUT_PORT,(UCHAR)(Pdx->IecOutEor ^ Pdx->IecOutBits)); } while (0)
68 #define CBMIEC_SET_RELEASE(_set,_rel) do { DBG_ASSERT((_set) != 0); DBG_ASSERT((_rel) != 0); Pdx->IecOutBits|=(_set); Pdx->IecOutBits&=~(_rel); \
69 WRITE_PORT_UCHAR(OUT_PORT,(UCHAR)(Pdx->IecOutEor ^ Pdx->IecOutBits)); } while (0)
72 #define CBMIEC_ARE_OUTPUT_LINES_CORRECT() ( READ_PORT_UCHAR(OUT_PORT) == (UCHAR)(Pdx->IecOutEor ^ Pdx->IecOutBits) )
75 #define CBMIEC_GET(_line) (((READ_PORT_UCHAR(IN_PORT) ^ Pdx->IecInEor) & _line)==0?1:0)
181 DbgWp(IN PUCHAR Port, IN UCHAR Value);
184 DbgRp(IN PUCHAR Port);
211 #define READ_PORT_UCHAR(_x_) DbgRp(_x_)
221 #define WRITE_PORT_UCHAR(_x_, _y_) DbgWp(_x_, _y_)
232 #define cbmiec_show_state(_x_, _y_)
243 cbmiec_i_raw_read(IN PDEVICE_EXTENSION Pdx, OUT UCHAR *buf, ULONG cnt, OUT ULONG *pReceived);
246 cbmiec_i_raw_write(PDEVICE_EXTENSION Pdx,
const UCHAR *buf, ULONG cnt, ULONG *pSent, BOOLEAN atn, BOOLEAN talk);
275 cbmiec_dpc(IN PKDPC Dpc, IN PDEVICE_OBJECT Fdo, IN PIRP Irp, IN PVOID Context);
277 #endif // #ifdef USE_DPC
VOID cbmiec_udelay(IN ULONG howlong)
Wait for a timeout.
ULONG T_1_RECV_WAIT_CLK_LOW_DATA_READY_GRANU
= 20 us: Starting reception, granularity for the wait until CLK is low
IEC_TIMEOUTS libiec_global_timeouts
enum cablestate_e CABLESTATE
@@@
ULONG T_11_SEND_BEFORE_BYTE_DELAY
= 50 us: Extra wait before sending of every single byte
ULONG T_15_SEND_BEFORE_BIT_DELAY_T_S
= 70 us: Inter-bit wait time while sending a byte
ULONG T_10_SEND_BEFORE_1ST_BYTE
= 20 us: Extra wait before sending 1st byte
NTSTATUS cbmiec_i_raw_write(PDEVICE_EXTENSION Pdx, const UCHAR *buf, ULONG cnt, ULONG *pSent, BOOLEAN atn, BOOLEAN talk)
Write some bytes to the IEC bus.
ULONG T_14_SEND_AT_END_DELAY
= 100 us: Extra wait after sending a block
ULONG T_12_SEND_AFTER_BYTE_DELAY
= 100 us: Extra wait after sending every single byte
ULONG T_17_SEND_FRAME_HANDSHAKE_T_F
= 100 us: Granularity: How long to wait for a frame handshake after sending a byte ...
ULONG T_5_Times
x T_5, is 200: How long to wait for CLK high (=active) for every single bit
ULONG T_16_SEND_BIT_TIME_T_V
= 20 us: How long to hold CLK low for every bit while sending
ULONG T_17_Times
x T_17, is 20: How long to wait for a frame handshake after sending a byte
ULONG T_9_SEND_WAIT_DEVICES_T_AT
= 10 us: Granularity: On send, how long to wait for driver to set DATA
enum cablestate_e CABLESTATE
remember in which state the cable is currently
struct IEC_TIMEOUTS IEC_TIMEOUTS
cablestate_e
remember in which state the cable is currently
VOID cbmiec_show_state(IN PDEVICE_EXTENSION Pdx, IN UCHAR *Str)
Dump the input lines.
Definitions for the libiec library.
ULONG T_holdreset
= 100 us: How long is a RESET being held?
ULONG T_5_RECV_BIT_WAIT_CLK_HIGH
= 10 us: Granularity: How long to wait for CLK high (=active) for every single bit ...
ULONG T_6_Times
x T_6, is 100: How long to wait for CLK low again (=inactive) after every single bit ...
ULONG T_WaitForListener_Granu_T_H
= 10 us: Graunularity of wait_for_listener() polls
ULONG T_4_Times
x T_4, is 100: Wait for CLK high after an EOI
ULONG T_PARALLEL_BURST_READ_BYTE_HANDSHAKED
= 300ms, timeout for reading one handshaked byte with parallel burst
ULONG T_4_RECV_WAIT_CLK_HIGH_AFTER_EOI_GRANU
= 20 us: Granularity: Wait for CLK high after an EOI
ULONG T_2_RECV_WAIT_CLK_HIGH_T_NE
= 10 us: Granularity: How long do we wait for the data of the other site
VOID cbmiec_schedule_timeout(IN ULONG howlong)
Schedule a timeout.
ULONG T_8_IEC_WAIT_SHORT_DELAY
= 10 us: For cbmiec_iec_wait(): Granularity (short)
ULONG T_7_RECV_INTER_BYTE_DELAY
= 70 us: Inter-byte delay on reception
ULONG T_3_RECV_EOI_RECOGNIZED
= 70 us: How long to set DATA to ack an EOI
NTSTATUS cbmiec_i_raw_read(IN PDEVICE_EXTENSION Pdx, OUT UCHAR *buf, ULONG cnt, OUT ULONG *pReceived)
Read some bytes from the IEC bus.
LONG cbmiec_i_pp_read_debounced(IN PDEVICE_EXTENSION Pdx)
Read a byte from the X[M|A]P1541 cable. Make sure to debounce it.
VOID cbmiec_show_port(UCHAR *s)
show the value of parallel port lines
VOID cbmiec_block_irq(PDEVICE_EXTENSION Pdx)
Block all interrupts.
ULONG T_afterreset
= 5 s: How long to delay after a RESET
ULONG T_6_RECV_BIT_WAIT_CLK_LOW
= 20 us: How long to wait for CLK low again (=inactive) after every single bit
VOID cbmiec_setcablestate(PDEVICE_EXTENSION Pdx, CABLESTATE State)
Set the current state of the cable detection.
ULONG T_13_SEND_TURN_AROUND_LISTENER_TALKER_T_TK
= 20 us: On listener-talker-turnaround, how long to wait until CLK is released
UCHAR DbgRp(IN PUCHAR Port)
Read from a port address with debugging output.
ULONG T_PARALLEL_BURST_WRITE_BYTE_HANDSHAKED
= 300ms, timeout for writing one handshaked byte with parallel burst
ULONG T_9_Times
x T_9a, is 100: On send, how long to wait for driver to set DATA
VOID DbgWp(IN PUCHAR Port, IN UCHAR Value)
Write to a port address with debugging output.
VOID cbmiec_release_irq(PDEVICE_EXTENSION Pdx)
Release the interrupts.
ULONG T_8_IEC_WAIT_LONG_DELAY
= 20 us: For cbmiec_iec_wait(): Granularity (long)
ULONG T_2_Times
x T_2 is 40